1. Field of the Invention
The present invention relates to the control memory organization in a microprogrammed data processing system.
2. Description of the Prior Art
A microprogrammed data processing system performs each program instruction by executing a microprogram, that is, a sequence of microinstructions stored in a control memory. Each microinstruction is executed in a machine cycle during which it generates signals or microcommands controlling the switching on/off of logical gates, the loading of machine registers and so on, that is, the operations of the logic elements which constitute the data processing system.
Each program instruction to be performed requires the independent control of a certain number of logic elements in sequence in order to allow the data processing system to execute the instruction. The microinstruction capability to independently control the logic elements of the system depends on the number of bits which constitute the microinstruction, that is, on the length of the microinstruction. The greater the length of the microinstruction, the greater the number of logic elements which must be controlled. Within some limits, the design may reduce to a minimum the length of the microinstructions (serial development of the instructions) or to increase the length of the microinstruction (parallel development of the instructions).
The serial development of the instructions involves the use of control memories with reduced word length and a smaller number of total bits. It therefore has the advantage of using less expensive memories, but also the disadvantages of increasing the instruction execution time and of deteriorating the system performance.
The parallel development of the instructions reduces to a minimum the instruction execution time, but it requires a longer word length of the control memory and an increased number of related circuits. This requires a greater memory capacity which is more expensive.
In relation to these aspects and to the fact that the several instructions have different requirements as to sequential operations to be executed and logic elements to be controlled, as well as different frequency of use, it is convenient to have control systems with a variable word length. In such a way, even though the total control memory capacity is limited, it is possible to use the longer word length for those program instructions which are frequently used and/or require the control of a large number of logic elements.
Several solutions have been proposed to achieve this result. In one prior art microprogrammed control system a main control memory with N addressable locations is coupled in parallel to a secondary control memory with M (M&lt;N) addressable locations. The two memories, for addresses less than M, are addressed in parallel and supply together a microinstruction of word length equal to the sum of the word length of the two memories. For addresses greater than M, only the main control memory is addressed providing microinstructions of length equal of its word length.
This solution has the disadvantage of limiting the possibility of expansion of the microinstructions to a determinate set of possible addresses of control memory and imposes a strict limit as to the allocation of the microprograms. In fact, all the microprograms including microinstructions longer than the word length of the main control memory must be stored into a prefixed memory zone; alternatively, the access to such microinstructions can be obtained by means of jump microinstructions stored in another memory zone, but this involves an increase of the memory capacity and a deterioration of performance.
U.S. Pat. No. 4,251,862 entitled "Control Store Organization in a Microprogrammed Data Processing System" describes a microprogrammed control system wherein a main control memory with N addressable locations is coupled to a secondary control memory with M (M&lt;N) addressable locations. A microinstruction read out from the main memory may specify through a suitable bit field representative of an address of the secondary memory and a key bit that the successive microinstruction must be expanded.
In this case, besides the addressing of the main memory for the reading out of the successive microinstructions, the secondary memory is addressed for reading out a binary code representative of the microinstruction expansion. In this way, a longer microinstruction is obtained to the detriment of a certain reduction in length of the previous microinstruction.
This solution has the advantage of allowing the microinstruction expansion in any memory location, but it presents other disadvantages, the most serious of which is that the system is incompatible with the requirement present in the control systems of interrupting the execution of a microprogram for executing a higher priority microprogram. In fact in data processing systems, it is generally provided that a program for performing an internal calculation or a program for processing a slow peripheral unit service may be interrupted at any time for the execution of operations required by a high speed peripheral unit, for example, a disk unit. The interruption is generally acknowledged during a machine cycle, that is, a microinstruction cycle.
It may occur that, during the execution of a microinstruction recalling an expansion code for the successive microinstruction, a microprogram interruption takes place. In that case, the microinstruction executed immediately afterwards is the first microinstruction of the interrupting microprogram and the expansion code is erroneously coupled to it.
Another disadvantage is present if the system has to be modified, that is, constituted at least partially by read/write memories. In such a case, it is necessary that both the main memory and the secondary one be read/write memories, otherwise the expansion code cannot be modified. This involves the necessity of using logical write control circuits for both memories with the result that the circuital complications and the cost increase.
The above disadvantages are overcome by the control memory organization of the present invention which permits variable length microinstructions able to fulfil different operative requirements which nevertheless have to be consistent with the possiblity of microprogram interruption.